Learning to verify branching time properties
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We present a new model checking algorithm for verifying computation tree logic (CTL) properties. Our technique is based on using language inference to learn the fixpoints necessary for checking a CTL formula instead of computing them iteratively as is done in traditional model checking. This allows us to analyze infinite or large state-space systems where the traditional iterations may not converge or may take too long to converge. We allow fairness constraints to be specified for verification of various liveness properties. The main challenge in developing a learning based model checking algorithm for CTL is that CTL properties express nested fixpoints. We overcome this challenge by developing a new characterization of CTL properties in terms of functions that have unique fixpoints. We instantiate our technique to systems in which states are encoded as strings and use a regular inference algorithm to learn the CTL fixpoints. We prove that if the fixpoints have a regular representation, our procedure will always terminate with the correct answer. We have extended our Lever tool to use the technique presented in this paper and demonstrate its effectiveness by verifying a number of parametric and integer systems.
Keywords Verification - CTL - Learning
A preliminary version of this work appeared in the proceedings of the twentieth IEEE/ACM International conference on Automated Software Engineering, Long Beach, California, USA, 2005.
Part of the work was done when the first author was at the University of Illinois.
Supported in part by DARPA/AFOSR MURI Award F49620-02-1-0325 and NSF 04-29639.
BibTeX
@article{journals/fmsd/VardhanV07,
author = "Vardhan, Abhay and Viswanathan, Mahesh",
title = "Learning to verify branching time properties",
ee = "http://dx.doi.org/10.1007/s10703-006-0026-x",
journal = "Formal Methods in System Design",
keywords = "formal methods, software engineering",
number = "1",
pages = "35-61",
volume = "31",
year = "2007",
}